In general, when losses of signals through a semiconductor substrate during a CMOS process are large, it is very important how to prevent circuits from distorting by interference of the semiconductor substrate.
Various studies on methods of overcoming interference between circuits during a CMOS process by connecting a wire connected to the AC ground in a ring shape or developing a process such as deep-n-well (DNW) are being actively made.
The most well-known method of preventing interference between circuits is to additionally provide an AC ground such as a P+ guard ring or an N+ guard ring around the circuits.
In a compound semiconductor process, the conductivity of a semiconductor substrate is very low as compared with that of a complementary metal oxide semiconductor (CMOS) process, and devices are physically isolated well from each other as compared with those manufactured by the CMOS process, such that interference between devices is not an important factor as compared with that of a CMOS process based design.
However, in recent, as the integration degrees and operation frequencies of circuits increase even in compound semiconductor processes, the interference between the circuits owing to transmission of signals through two close wires needs to be considered when the circuits are designed.
The characteristics of a circuit having two wires in parallel are clearly different from those of a circuit having two independent wires. In order to express this phenomenon in simulation, various circuit simulators for RF related designs, in particular, simulators analyzing signals through electro-magnetic (EM) analyses analyze how the interference between such wires is caused.
When the interval between wires becomes narrower as the operation frequency of an integrated circuit increases, the electromagnetic interference between micro-strip lines needs to be considered, and if the integrated circuit is designed and laid out without considering the electromagnetic interference, its efficiency may be unexpectedly deteriorated.
In other words, as the integration degree of an integrated circuit, in particular, the number of simple circuit blocks increases and demands for designs of complex asymmetric circuits increase, the interference shortcomings cannot be solved only by isolating the circuit blocks and widening the interval between the circuit blocks.
In particular, in a layout of a circuit having an asymmetric amount of power or phase thereof, the deterioration of the circuit owing to interference between wires is considerably problematic in a compound semiconductor process.